A Decade of SystemVerilog: Unifying Design and Verification?

It’s hard for me to believe that SystemVerilog 3.1 was released just over 10 years ago. The 3.1 version added Object-Oriented Programming features for testbench development to a language predominately used for RTL design synthesis. Making debug easier was one of the driving forces in unifying testbench and design features into a single language. The semantics for evaluating expressions and executing statements would be the same in the testbench and design. Setting breakpoints and stepping through the code would be seamless. That should have made it easier for either a verification or a design engineer to understand a complete verification environment. Or maybe it would enable either one to at least understand enough of the environment to isolate a particular problem.
Ten years later, I have yet to see that promise fulfilled. Most design engineers still debug their simulations the same way they debug in the lab: they look at waveforms. During simulation, they rarely look at the design source code, and certainly never look at the testbench code (unless it’s just basic pin wiggling like a waveform). Verification engineers are not much different. They rely on waveform debugging because that is what they were brought up on, and many do not even realize source-level debugging is available to them. However the test/testbench is more like a piece of software than a hardware description, and there are many things about a modern testbench that is difficult to display in a waveform (e.g. call stacks, local variables, and random constraints). And methodologies like the UVM add many layers of source-level complexity that most users do not have the time to wade through.

UVM 1.2: Open Public Review

UVM 1.2 Release is Imminent

As vice chair of DVCon 2014, I can share with you that the Universal Verification Methodology (UVM) remains a topic of great interest. It sets the pace for tutorials and given the pending release by Accellera, learning what is new in UVM 1.2 is a compelling reason to attend DVCon.
The Accellera Day tutorial series on Monday at DVCon is popular with UVM being a session of great interest. Aside from the “verification crisis” driving the need to explore this industry standard, the first major update is also a reason to generate this interest. The UVM tutorial is meant for the novice and expert alike. UVM experts can expect to walk away with more information on the new UVM 1.2 features and how they might plan to deploy them.
Naturally, I suggest you consider registering for the conference to attend this tutorial. (There are still a few seats left; but you will need to hurry!)

UVM Working Group Discussions

As a member of the Accellera UVM Working Group, I have asked the team to consider adopting the SystemC development scheme of an open public review of a pending release of open source code. While the merger of OSCI and Accellera to form Accellera Systems Initiative inherited the OSCI style of public review, Accellera has not fully embraced it for all its projects.
In a disclosure of a bit of insider conversation I had with the UVM WG this last week, I asked the group to confirm that we were going to bypass the “official” public review option and go to an internal 30-day review cycle only – then release to the public. While the conclusion was to stay on the 30-day internal review path, the group also noted that one who may be familiar with Git might be able to locate the source code (and many have) and do testing.
Since the bleeding-edge users know they can access as it is being developed, why not share the Git commands for everyone to gain access? So the group has done just this. When last minute changes for Release Candidate 4 were put in place, the Git script to offer access for early review was shared publicly. You can find can find this public message here, thanks to UVM WG member Adiel Khan (from Synopsys).
If you are a seasoned UVM user and are attending DVCon the week of March 3rd, I would encourage you to do some testing now so you can connect with the developers first hand. And even if you are not attending DVCon but want to migrate to UVM 1.2, you might want to get an early start to determine what you might need to do to adopt this release.
If you are not going to attend the DVCon UVM tutorial and want a short update on what this version will offer, the UVM WG secretary, Adam Sherer (from Cadence), put together a brief slide set that he presented at the TVS DVClub event in September 2013 that you can download. You may find it a useful companion to the download of the open source code.
Even if you are not attending DVCon, the adoption of UVM is globally substantial and it might be good to reflect on the need for broader testing. In the first releases of UVM, this may not have been as important as few were using it and the number of tests limited to the main developers. However, as its popularity has grown and adoption increased, it is probably a good idea for the Accellera UVM Working Group to consider the impact of a new release on teams actively using it now. While the UVM WG drives to closure on its release candidate and the UVM 1.2 standard, you are offered the opportunity to give us feedback. For those who have time, please do!

Mentor Commentary on Standards Development

Lastly, for those attending DVCon, check out our own Tom Fitzpatrick’s Wednesday morning paper – Of Camels and Committees: Standards Should Enable Innovation, Not Strangle It. His commentary on the development process may shed some additional light into how technology additions, changes and enhancements are judged for inclusion in updates to standards, like UVM

Accellera Approves UVM 1.2

Accellera has announced the completion of a multi-year effort to update its latest edition of the Universal Verification Methodology (UVM). In completing this effort, the UVM 1.2 Class Reference Document was approved as an Accellera standard and the UVM Working Group has supplied an accompanying open-source reference implementation. Questa supports UVM 1.2.
In addition to the resources you can download from Accellera, additional information on UVM 1.2 can be found at the Verification Academy. HTML documentation can easily be found at the Verification Academy too.
If you are a user of UVM 1.1 and have not been part of the UVM 1.2 development effort, you should know your peers have been busy the past few years since the stabilization and completion of UVM 1.1 to drive global adoption of UVM and to add, enhance and extend UVM. In UVM 1.2 Messaging is now object-oriented, Sequences can automatically raise and drop objects, the register layer can now control transaction order within bursts and numerous bugs in UVM 1.1 have been fixed to improve quality.

Backward Incompatibility

All these changes come with a cost to the current UVM 1.1 user community. When Accellera announced UVM 1.2 availability, it also disclosed some of the new features introduce backward incompatibility. To reduce those issues, Accellera is making release notes and a one way conversion script part of the UVM 1.2 kit to ease the migration path forward.
If you follow the Verification Academy Cookbook rules, you will probably not see any impact from the backward compatibility issues. And if you control your total verification environment, you will probably find it simpler to migrate forward as well. Those who depend on outside resources will need to make sure those resources (like Verification IP) migrate forward to UVM 1.2 so you can migrate forward to UVM 1.2. Mixing UVM 1.1 and UVM 1.2 was not considered by the Accellera UVM Working Group and is fraught with unknown issues. We consider the migration an all or nothing proposition. If you have multi-division, multi-company projects underway, it would be prudent to plan you move to UVM 1.2 with care at the conclusion of projects and when all suppliers and participating teams can migrate to UVM 1.2.

Public Review Period

Accellera seeks your input and feedback on UVM 1.2. To support this, a public review forum on the Accellera website has been established to allow users to catalog issues, ask questions and generally offer feedback to help improve UVM 1.2 quality.
The public review process will end on October 1, 2014. We encourage users to take the time now to test UVM 1.2 in their own environments and share their feedback to expidite the migration to UVM 1.2.

Path to IEEE

Public feedback will be taken into account along with further Accellera member testing to update UVM 1.2 prior to a committed hand-off to the IEEE for further standardization there later this year. As this path unfolds, I will share updates on the standardization effort in the IEEE.

Verification Academy DAC 2014 UVM 1.2 Presentation

You will find many resources around the world on UVM 1.2. At DAC 2014, the Verification Academy booth sponsored a session on UVM 1.2 titled “UVM: What’s New, What’s Next, and Why You Care.” If you did not attend DAC, you can still download the presentation and watch a video replay of it if you are a Verification Academy “full access” member (free registration required; restrictions apply).
The presentation by Tom Fitzpatrick goes into detail on the UVM 1.2 topic. Importantly in Tom’s presentation is a discussion about what you should care about today. You may find that software is a big issue and that his thesis challenges one to ask if UVM 1.2 is stuck in the past rather than addressing what should be addressed next. I invite you to download the presentation and watch the video and share with me your thoughts. What do you think?