Accellera Adopts OVM 2.1.1 for its Universal Verification Methodology (UVM)

This was a productive week for Accellera. After months of discussions, the Accellera Verification IP Technical Subcommittee (VIP-TSC) voted to adopt OVM 2.1.1 as the base of its verification methodology. Accellera’s OVM version will be called UVM.
In adopting OVM 2.1.1, Accellera signaled it will make further changes. The VIP-TSC has approved changes to (1) modify file names that have OVM in them to UVM, (2) modify any function calls and element names from “ovm” to “uvm,” (3) make possible changes to the “end-of-test” and “callback” code found in OVM 2.1.1, and (4) add a “message catching” feature.
This is good news for Accellera and great news for those who have adopted OVM and use OVM today. I believe OVM users will find it easier to interoperate with this third methodology. As a strong supporter of Accellera standards, we will keep you updated on Accellera UVM as developments merit. Users should expect solid industry support in all their popular tools as the Big-3 EDA suppliers have all voiced public support for this standards project.

Motivation for the UVM

In the beginning, there was SystemVerilog, and it was good. Through it some testbenches were made; without it other testbenches were made. In SystemVerilog was light, but also darkness in the form of a set of missing features that had to be implemented as library on top of verification languages by each user and also in the form of a lack of interoperability of language features between simulators.
To address the missing features there came a verification methodology sent from Synopsys; its name was VMM. The URM from Cadence and the AVM from Mentor came also and later merged to form the OVM, so that through them all engineers might believe in verification libraries.  The libraries did not completely address users’ concerns, but they did serve to validate users’ concerns as valid and worthy of consideration.
The libraries were the solution, and though the solutions were made through them the verification community did not recognize them as the solution because interoperability had not been solved.
Cool Verification 1:1-15 … ;-)
Ahem… As many of you are aware, the Accellera Verification IP Technical Subcommittee (VIP TSC), is currently working on creating a unified universal verification methodology (UVM) that will be supported by the big three EDA vendors.  Ostensibly the library is being created so that users don’t have to make a (potentially limiting) choice between the OVM and VMM, but can instead use a library that is considered an industry standard. Sounds good, right? I’m going to make the potentially controversial claim that very few semiconductor companies actually care about using an industry standard methodology.

Purchasing managers have largely bought into the fallacy that by using SystemVerilog they can easily switch vendors should they choose to do so. But language support between the vendors is still different enough to make it challenging to maintain code for more than one simulator. Vendors have been resistant to publicly sharing the level of support their simulators have for the SystemVerilog language, and no independent comparison is possible due to onerous licensing restrictions.
The VIP TSC will be meeting face to face the second week of March to work out the requirements for the UVM development effort. If my suspicions prove accurate, a lot of time and energy will be spent debating the fine points of verification methodology architecture, but the end result may be no closer to helping the average verification engineer solve the most pressing issues they face. But as usual, I am happy to be proven wrong. is the UVM's purpose to finally solve the SystemVerilog cross-methodology interoperability problem once and for all, or is it a red herring to distract us from the still elusive goal of a vendor independent tool flow...

Scalability Made OVM The Ideal Choice For UVM

The popularity of OVM that made it the idea choice for Accellera's UVM is rooted in it's uniquely scalable architecture.  Today's announcement by Mitsubishi Electric and the OVM Advanced Topics tutorial at DVCon are examples of scalability beyond the common SystemVerilog testbench.
For some verification teams, jumping head-first into the maw of object-oriented programming is daunting.  Object-oriented programming does require a series of fundamental shifts in thinking including writing code for objects that will come in and out of existance during simulation, the ability to override types to localize VIP rather than rewriting it, constrained-random inputs, and more.  For engineers that have built directed testbenches for years, aquiring all of this knowledge and applying it while maintaining schedule and quality commitments is a daunting task.  Mitsubishi found that the module-based overlay provided by Cadence enables the full OVM methodology while creating a static strucure that makes implementing the first object-oriented testbench easier.
At the other end of the scalability spectrum are the OVM Advanced Topics.  Among these are multi-langauge support for e and SystemC, low-power verification using OVM sequences to set-up power-states in the DUT, acceleration for verification performance, and ABV to both utilize assertions with OVM and to include formal analysis in an overall metric driven verification methodology that includes formal. At DVCon on Tuesday February 23rd Cadence verification experts will lead an interactive tutorial on these advanced topics so be sure to register early!
So with the UVM coming soon, how will OVM and future UVM users access all of this advanced technology? First, all of the advanced topics work with the existing OVM 2.1 release so we expect that they will work with UVM 1.0 as it will be based on OVM.  Second and more importantly, many of these are available to users right now in the OVM World contributions area.  If any of these are interesting to you and you want them to be included in the UVM 1.x releases, please contact your Accellera rep or join the VIP TSC and make your wishes known!

Accellera Works Toward a Unified Verification Methodology (UVM)

Accellera believes that the release of its UVM document is only a couple of months away. Can this really be true?
Design verification, in all of its various stages, continues to be a costly and challenging task, in spite of efforts dating back to the 1980s to provide engineers with better design tools. A quarter of a century after the introduction of Verilog and VHDL, languages meant to simplify the description of a design and thus ease the verification burden, costs continue to rise. Silicon respins due to design errors not only have not diminished in number, they have actually increased. This is an indication that complexity has grown more than the ability of verification tools to detect errors.
EDA tools developers have known for some time that not only tools need to be improved, but design methods also need to become more verification aware. So, in the usual highly competitive manner the EDA industry loves, a couple of years ago Cadence and Mentor agreed to develop together a verification methodology for SystemVerilog and called it: OVM which stands for Open Verification Methodology. Of course the word "open" in EDA does not mean freely available and thus Synopsys, who felt excluded from such "openness", insisted with VMM which stands for Verification Methodology Manual. VMM development started as early as 2005 when Synopsys partnered with ARM on the project. So one can safely state that OVM was a response to the lack of "openess" on the part of Synopsys toward allowing the other big two in the game without a price (and why should they?). How provincial EDA must seem to our major users! As you can imagine EDA customers were thrilled at the prospect of another war similar to the Verilog/VHDL wars of twenty or so years ago.
Accellera, the industry standard organization who has demonstrated a willingness to go where no one has gone before, acknowledged the problem and started a Technical Subcommittee with the aim of developing a unified methodology, called UVM, for Unified Verification Methodology.
As the year 2009 was coming to a close, the Technical Subcommittee (TS), at the prodding of "the elephant in the room" that answers to the name of Intel, reached a breakthrough, or so it seems, when Cadence, Mentor, and Synopsys agreed to begin a focused technical work project aimed at unifying the two methodologies. Some of the marketing representatives at Synopsys and Cadence have told me they expect the release of UVM in March this year. As should be expected the unrestrained joy in the streets of the silicon designers and providers should be restrained by appropriate skepticism..
The Details Make Things Difficult
As with every engineering task, the details are getting in the way of rapid progress. To begin with, the agreement was reached by a majority vote, meaning that not everyone was in favor of the motion as written. The problem, according to Mentor is in the timing. The present version of OVM is 2.0.3. It seems that OVM 2.1 was only a week or so away from being released. Yet, according to Synopsys, it is OVM 2.0.3 the version that will be used as the basis for the TS work. Mentor is pointing out the obvious: why disregard the work done to develop the 2.1 version?
Synopsys says that "We need to start with something and build on it. As a base OVM 2.0.3 will serve to create more features and improve users productivity". So, what is new in OVM 2.1 is not discarded a priori, it is just up for review. But when you ask Cadence which version of OVM will be used to create UVM, they say OVM 2.1, because it is released and it does not make sense to go back. Tom Anderson, Product Marketing Director for Verification Software at Cadence expects that OVM world, the association of OVM users, will continue to exist and that it will concern itself with both OVM and UVM topics.
One of the aspects of this work that holds positive, yet unexpected, outcome is that UVM will need to fully harmonize with the TLM specification from OSCI. Although there are many common members of the two organizations, there has never been a formal, structured, cooperation method between Accellera and OSCI. The development of UVM might give both Accellera and OSCI a real opportunity to put together a structure aimed at harmonizing each other's work, to the significant benefit of the EDA industry.
From a political point of view, the person that should be the principal architect of UVM is also a significant obstacle to speedy progress. Janick Bergeron, the architect of VMM, is a well known SystemVerilog and verification expert, and happens to be a Synopsys employee. Since the aim is to take OVM as the base and enrich it with VMM features, Cadence and Mentor expect that the chief architect will be someone who is intimately familiar with OVM, and that person is not Janick.
The final hurdle I am aware of is the matter of the license. OVM is distributed as open source under the Apache style license. Accellera has never developed a standard that is open source, it kind of runs against the idea of "standard". There seems to be significant belief within the interested parties that such issues are manageable. To begin with the matter of what is standard in an open source environment can be easily handled. What Accellera will release is the standard. People are free to add to it but not modify it under the open source environment. The additions will then be considered for inclusion in a later version of the standard. This seems to be a minor problem.
What Will Make the Job Easier
In most cases, like when you need to develop a language or a format, the standard needs to be firmly adhered to and no changes can be tolerated. But OVM, VMM and thus UVM are libraries, and so it is possible to have a standard base library and not only additional capabilities contributed by the open source community, but also OVM and VMM features that would have been deprecated (made obsolete) by the standard, and which are used by customers, that do not survive the merger.
Cadence, Mentor, and Synopsys all have major customers that, just like Intel, need a unified methodology. Here money talks loud and thus the desire of the three vendors to satisfy their customers is great. It must be noticed that the vote to start UVM came at the end of a fiscal quarter, a time when license renewals are discussed with great attention.
Finally no one has suggested forming yet another consortium to get the job done. Accellera has, with the exception of the IEEE, the best experience in EDA in developing lasting standards that span the gamut of all EDA market segments. The job will get done, the standard will be robust, and if not by March, it will be here by June, in time for DAC.

UVM: Collaboration for the Right Reasons

Congratulations to Accellera’s Verification IP Technical Subcommittee (VIP-TSC) for reaching yet another milestone on its journey to achieve harmony among verification standards. The near-unanimous desire and commitment to create a Universal Verification Methodology is an indication of the still growing need for collaboration among verification engineers, verification IP vendors, service providers, and tool suppliers – and their faith in Accellera to do so as an open standards organization.
Now it’s time for the group to start working on their “long term” standard. Their efforts will produce a common base class library that can be used in simulators from multiple design automation tool vendors. The common base class library will foster a broad (universal) verification methodology to benefit verification engineers and developers of verification IP.
The VIP-TSC will provide the industry with an effective verification standard. Hmm. Maybe they will call it the Universal Verification Methodology (UVM).
According to the status report from the VIP-TSC, the next phase of their work is indeed called the Universal Verification Methodology (UVM)!!
And now it’s time for the group to start working on their “long term” standard. Their efforts will produce a common base class library that can be used in simulators from multiple electronic design automation tool vendors. The common base class library will foster a broad (universal) verification methodology to benefit verification engineers and developers of verification IP.
The VIP-TSC working group that will now tackle UVM appears to be focused on a critical aspect of standardization – delivering not only a specification but also a usable reference implementation. In the short-term phase of their work, they created an interoperability guide, and now they will work on providing a single UVM library that will reflect the best of VMM and OVM. This is what I like about an industry collaboration that’s focused as much on deployment of a standard as it is on the creation of it.
This open, inclusive, and timely standard coming to life with support from a wide-ranging verification community. Synopsys strongly endorses this UVM effort under Accellera. I encourage the committee to ensure that UVM not only meets immediate requirements but also builds the foundation of an industry-wide verification methodology for years to come.
Overall, big kudos to the working group  for their focus on the long term goals, their dedication, and their hard work. It’s a great way to start 2010!

Behind Accellera’s Vote For OVM-Based Standardization

As noted in a recent Cadence blog by Tom Anderson, the Accellera Verification IP (VIP) Technical Subcomittee has voted to make the Open Verification Methodology (OVM) the basis of its upcoming “Universal Verification Methodology” (UVM) standard. Here are some thoughts about what this means, why it’s important, and what questions will need to be answered as the UVM standard unfolds.
First, why is a methodology needed? Because the SystemVerilog language description alone does not tell you how to build testbenches or verification IP. Thus, early SystemVerilog users developed in-house methodologies. Synopsys then launched the Verification Methodology Manual (VMM), and Cadence and Mentor Graphics collaborated to produce OVM, which is now available from the very active OVM World web site.
With two different methodologies in the marketplace, many users were faced with having to juggle VMM and OVM VIP and/or testbenches in the same simulation environment. Amid widespread agreement that standardization was needed, the Accellera VIP committee was formed. It was launched with two goals:

• Interoperability between VMM and OVM, which is provided by last year’s release of a Recommended Practices interoperability guide. It shows how VMM testbenches can work with OVM VIP, and vice versa.
• Progress towards a single SystemVerilog methodology standard with a common base class library, with eventual IEEE standardization. This is currently referred to as “UVM.”

That said, the development of UVM is just beginning and there are many questions to be answered over the coming weeks and months. For example:

• Will UVM be a superset of OVM, including all OVM capabilities?
• OVM World participants have made some good contributions to OVM. Will Accellera include some of these in UVM?
• Will UVM offer seamless backwards compatibility with existing OVM VIP?
• How can users migrate VMM testbenches or VIP to the new standard?
• While Accellera is only looking at SystemVerilog, OVM can work with the e testbench language and SystemC models. Will UVM ultimately support multiple languages?

As noted in a recent blog, true VIP interoperability goes far beyond standard methodologies and class libraries. But a standard is essential for interoperability to be possible. With its latest decision to move forward based on OVM, the Accellera VIP subcomittee is making great progress towards solving the VIP interoperability challenge for SystemVerilog users.

UVM: Extending Standardization from Language to Methodology

 
For nearly 25 years, the standardization of design and verification languages has been an accepted part of the electronics industry. Although many early electronicdesign- automation (EDA) standards dealt primarily with the interchange between tools (for example, EDIF and GDS II), the majority of standards in use today define how design and verification engineers provide input to EDA tools. Widely used examples include the following: SystemVerilog, Verilog, Verilog-AMS, VHDL, and SystemC for designs and models; SystemVerilog and e for verification environments; SystemVerilog Assertions (SVA) and Property Specification Language (PSL) for assertions; and Common Power Format (CPF) and Universal Power Format (UPF) for power intent.
Some of these standards began as proprietary formats that were then standardized by the IEEE, Accellera, Si2, or other organizations. Others originated directly within these standards bodies. Either way, once a standard is available, users tend to gravitate toward it quickly. Design and verification engineers take it for granted that all EDA vendors will provide support as organizations define new standards and existing ones evolve. Naturally, there’s always an adoption curve as vendors implement support and users come up to speed on each new language. But everyone involved in EDA accepts the need for language standards and ultimately embraces them.
Until very recently, however, methodology wasn’t subject to standardization. Engineers who learn standard languages quickly realize that there’s more to being successful than just knowing the constructs in the Language Reference Manual (LRM). Designers need to learn how to specify their designs in a style that works well for synthesis and results in an implementation that meets their area, timing, and power requirements. Verification engineers need a great deal of guidance in order to construct environments that are efficient and effective. Design and verification reuse from project to project—or even between companies—places further demands on methodology.
METHODOLOGY EVOLUTION
Recognizing that successful usage goes beyond the constructs defined in the LRM, some standards bodies also provide user guides. These guides offer more detailed code examples while discussing basic issues of methodology. Particularly when it came to verification, however, no existing standard even attempted to tackle the complete scope of the problem. The result was that some end users defined their own verification methodologies while the rest adopted the methodology developed by their primary EDA providers. In the specific case of SystemVerilog, the three major simulator vendors each developed their own independent verification methodology.
The history of verification methodology begins with Verification Advisor (vAdvisor), a collection of best practices for the e verification language developed in 2000 by Verisity Design (now part of Cadence). This led directly to the e Reuse Methodology (eRM) in 2002. Although the e language was standardized a few years later, the eRM wasn’t. Shortly thereafter, Synopsys introduced the Reference Verification Methodology (RVM) using its OpenVera verification language. Neither the methodology nor the language was ever standardized. In 2005, Synopsys published the Verification Methodology Manual (VMM) for SystemVerilog. In 2006, Mentor Graphics introduced the Advanced Verification Methodology (AVM), which was based on both SystemVerilog and SystemC. Cadence spanned all three verification and modeling languages by expanding the eRM into the Universal Reuse Methodology (URM) in 2007.
Although each of the three vendors’ methodologies had success within their own customer base, each ran only on its own simulator. There was no attempt at cross-vendor support or any form of standardization. The first key step in this direction happened in early 2008, when Cadence and Mentor delivered the first SystemVerilog version of the Open Verification Methodology (OVM). Like its AVM and URM predecessors, the OVM was provided as open source. But it was the first methodology to be tested and guaranteed to work on multiple simulators. Although the OVM has enjoyed wide adoption, it can be regarded only as a de facto standard because it wasn’t directly endorsed by any organization. This all changed with the 2010 introduction of the Universal Verification Methodology (UVM), which evolved directly from the OVM (see Figure 1).
Figure 1: Universal Verification Methodology (UVM) evolved directly from the OVM.
HISTORY OF THE UVM
The first serious industry attempt to standardize a verification methodology began in 2008, when the Verification IP Technical Sub-Committee (VIP-TSC) was formed within Accellera. It was already clear that the OVM would be very successful. Given its longer history, there were many VMM users as well. Thus, the initial focus for the TSC was to figure out how VMM-based VIP could function in an OVM verification environment (and vice versa). Cadence, Mentor, and Synopsys worked with representatives of numerous user companies to define and validate a standard interoperability solution to link the two methodologies.
The second focus for the Accellera TSC, which is still in progress, is to define the UVM—a single standard verification methodology supported by all major simulation vendors and meeting the diverse needs of the user community. After an extensive process of due diligence, in which many members presented their requirements for such a common methodology, the committee voted to base the UVM very closely on the 2.1.1 release of the OVM. The initial release, UVM 1.0 EA, came out in May of this year. It contains a few small additions beyond OVM 2.1.1, but otherwise is exactly the same methodology and building-block class library (with the “ovm_” references changed to “uvm_”). Thus, the initial UVM release is ready for production use. In fact, it has already been adopted by many projects.
Current Accellera plans call for a “UVM 1.0” release before the end of 2010. Exactly what additional features will be included is the subject of much debate at TSC meetings. But the chairs have pledged strong backward compatibility to ensure that current users can upgrade easily. The future of the UVM is bright with many possibilities for expansion over time. Cadence expanded the OVM to include e verification environments and SystemC models. It has pledged to do the same for the UVM for possible consideration by Accellera. Other potential areas for extension include low-power verification, mixed-signal simulation, simulation acceleration, and hardware-software co-verification.
ASPECTS OF UVM STANDARDIZATION
As the first methodology being standardized by any organization, the UVM is breaking new ground. However, its standardization process is a natural outcome of previous EDA standards. It’s important to distinguish the three key aspects of the UVM provided by Accellera: the building-block class library, Class Library Reference, and User Guide. Strictly speaking, the “standard” consists of only the Reference, as it defines the interfaces and functionality of the class library elements. Figure 2 shows an example of a UVM-compliant verification environment in which the components and the interfaces among them are defined by the library.
Figure 2: In this example of a UVM-compliant verification environment, the components and the interfaces among them are defined by the library.
Although the User Guide provides important supplemental information to construct such environments, it isn’t technically part of the standard. The library itself is regarded by Accellera as a reference implementation.