Microsoft présente une première version de Windows 8

La prochaine mouture de Windows, numérotée 8, a été dévoilée hier à la conférence des développeurs Build. Elle se fait remarquer par une double interface, l'une traditionnelle, semblable au bureau de Windows 7, pour les applications classiques sur ordinateurs de bureau, et l'autre fortement inspirée des appareils mobiles, donc de Windows Phone 7, prévue surtout pour les tablettes. Le nouveau système Windows acceptera les commandes provenant de surfaces tactiles, de stylos ou de la reconnaissance de gestes, comme sur le boîtier Kinect.

Microsoft a vanté mardi la versatilité de son prochain système d'exploitation Windows 8, qui pourra aussi bien faire fonctionner des ordinateurs que des tablettes, afin de mieux rivaliser avec l'iPad d'Apple. « Windows 8 fonctionne magnifiquement sur toute une gamme d'appareils, des tablettes aux ordinateurs portables de 10 pouces (25 cm de diagonale) et jusqu'aux ordinateurs tout-en-un avec des écrans haute définition de 27 pouces », s'est autofélicité le président de la division Windows de Microsoft, Steven Sinofsky, durant la conférence Build, destinée aux développeurs.

Le système doit notamment permettre de faire fonctionner plusieurs applications ensemble et de synchroniser les dossiers entre plusieurs appareils. En guise d'illustration, Steven Sinofsky s'est fait prendre en photo par une caméra montée sur ordinateur, et le cliché est apparu sur une tablette.

Une version encore expérimentale

Le géant de Redmond (État de Washington, nord-ouest des États-Unis) a offert des prototypes de tablettes aux 5.000 participants à la conférence afin qu'ils puissent commencer à travailler sur ce programme. Les développeurs ne participant pas à l'événement pourront télécharger une version préliminaire de Windows 8 disponible depuis cette nuit.

Steven Sinofsky a souligné qu'il s'agissait d'une version expérimentale, et pas d'un programme fini destiné à être diffusé en l'état auprès du grand public, et il s'est refusé à évoquer une date de lancement. « Nous nous laissons guider par la qualité, pas par le calendrier, et pour l'instant nous nous concentrons sur les applications », a-t-il dit.

Calypto Design Systems Acquires Mentor Catapult C Synthesis Tool

SANTA CLARA, Calif. August 26, 2011 – Calypto Design Systems today announced it has acquired Catapult C Synthesis from Mentor Graphics Corporation (NASDAQ: MENT). The merger of two market-leading electronic system level (ESL) products, Catapult C Synthesis and Calypto SLEC System-HLS verification tool, will create a better integrated ESL hardware realization flow, and enhance the company’s partnership with Mentor Graphics, a leader in ESL technology. Terms of the transaction were not disclosed.
”ESL synthesis offers our design community the next great leap in productivity. Much like the move to RTL years ago, the move to higher levels of abstraction based on C and SystemC offers the promise of better quality of results in a shorter amount of time. By combining the market leading products in C synthesis, sequential verification, and power optimization within Calypto, we will be the only company capable of delivering a fully integrated flow, and delivering on that promise of ESL,” said Doug Aitelli, Chief Executive Officer of Calypto Design Systems. “In addition, we remain fully committed to our existing high level synthesis partnerships and to industry-wide interoperability.”
“This is a great deal for Calypto,” said Gary Smith, Chief Analyst at GSEDA. “They are clearly one of the companies on the rise in ESL, and this gives them the chance to offer a compelling power-optimized C to RTL flow if they can integrate all the pieces.”
ESL methods allow designers to work at a higher level of abstraction, greatly reducing errors and allowing greater optimization of integrated circuits (IC) in key attributes like speed and power. To adopt ESL methods, designers need to have confidence that tools, as they translate from the higher level of abstraction to lower levels, don’t introduce errors. Typically, designers have used extensive RTL verification to ensure that no errors have been introduced.
SLEC System-HLS uniquely addresses this challenge with C to RTL formal equivalence checking using patented sequential analysis technology to create an easy to use synthesis and verification flow environment. Designers can perform comprehensive functional verification using SLEC System‐HLS to formally verify equivalence between SystemC ESL models and RTL implementations. This leads to up to 100x speed up times in RTL verification as it removes the need for significant and time consuming RTL simulation to validate that the RTL matches the C or SystemC source. Tight integration between Calypto’s SLEC System-HLS and Catapult C Synthesis will give designers confidence that the IC they designed in C or SystemC is the IC that is being delivered in RTL.
Additionally, the PowerPro SoC Power Reduction Platform can do RTL level power optimizations. Added to the Catapult C Synthesis and SLEC System-HLS hardware realization flow, this allows designers to swiftly go from C and System C designs to power-optimized RTL.
“We remain deeply committed to ESL. We view this transaction as an innovative way to accelerate adoption of ESL methodologies, to strengthen our partnership with Calypto, and as one that complements our continued investment in ESL virtual prototyping environments led by our Vista product,” said Brian Derrick, vice president of marketing at Mentor Graphics. “Calypto’s Sequential Logic Equivalency Checker is a critical and unique technology for enabling the adoption of ESL. Its combination with the market-leading Catapult C Synthesis product and the PowerPro SoC Power Reduction Platform, should give designers the confidence to adopt ESL methods and enjoy the significant benefits that designing at higher levels of abstraction brings.”
Current customers of the Mentor Graphics Catapult C Synthesis tool will continue to be supported by Mentor Graphics. Moving forward, any new customer sales and support will be supplied by Calypto.

About Calypto Design Systems
Calypto Design Systems, Inc. empowers designers to create high‐quality, low-power electronic systems by providing best‐in‐class power optimization and functional verification software, based on its patented Sequential Analysis Technology. Calypto, whose customers include Fortune 500 companies worldwide, is a member of the Cadence Connections program, the IEEE‐SA, Synopsys SystemVerilog Catalyst Program, the Mentor Graphics OpenDoor program, Si2, ARM Connected Community and is an active participant in the Power Forward Initiative. Calypto has offices in Europe, India, Japan and North America. More information can be found at: www.calypto.com.

Calypto Joins ARM Connected Community

SANTA CLARA, Calif., – July 20, 2011 -- Calypto® Design Systems, Inc., the leader in Sequential Analysis Technology, today announced it is a new member in the ARM® Connected Community, the industry’s largest ecosystem of ARM technology-based products and services. As part of the ARM Connected Community, Calypto gains access to a full range of resources to help it market and deploy innovative design platforms that enable developers to get ARM Powered® products to market faster.
Calypto’s SLEC® (Sequential Logic Equivalence Checking) and PowerPro® platforms are used by seven out of the top ten semiconductor companies and most leading consumer electronics companies. Calypto’s products enable electronic designers, including ARM customers, to dramatically improve design quality and reduce power consumption of their system-on-chip (SOC) devices.
“Our products help engineers improve the quality of their ARM hardening flow in two ways,” said Doug Aitelli, Chief Executive Officer at Calypto. “PowerPro reduces the power of the ARM processor and surrounding SOC, and SLEC provides a comprehensive formal verification of the RTL to make sure that no functional errors were introduced during the ARM hardening process. This verification eliminates the need to redesign testbenches and rerun exhaustive simulations, enabling ARM customers to tapeout SOCs with ARM intellectual property faster. As a member of the ARM Connected Community, we now have the opportunity to extend our reach and add value to more of ARM’s customers.”
 “The Connected Community is all about companies working together to provide the most complete solutions in the shortest possible time. By joining the Community, which now comprises more than 850 companies, Calypto increases the large portfolio of skills, products and services that are centered around the ARM architecture, and currently available to developers worldwide,” said Lori Kate Smith, Senior Manager Community Programs for ARM.
Calypto Verification and Power Consumption Benefits for ARM Connected Community
PowerPro CG is used to help ARM’s Connected Community reduce the power consumption of their ARM processors or the surrounding SOC design. Using Calypto’s patented Sequential Analysis Technology, PowerPro CG (Clock Gating) analyzes the design intent of the ARM processor and derives areas where additional clock gating can be implemented or improved. PowerPro then can be used to automatically or manually reduce the power consumption, and SLEC formally verifies the result. In addition, PowerPro MG (Memory Gating) reduces power in the memory sections of a design, creating controllers to shut off the memories for longer period of times. This saves dynamic power, through gating of the memory enable, or leakage power, through activation of light sleep mode.
About the ARM Connected Community
The ARM Connected Community is a global network of companies aligned to provide a complete solution, from design to manufacture and end use, for products based on the ARM architecture. ARM offers a variety of resources to Community members, including promotional programs and peer-networking opportunities that enable a variety of ARM Partners to come together to provide end-to-end customer solutions. Visitors to the ARM Connected Community have the ability to contact members directly through the website.
For more information about the ARM Connected Community, please visit http://cc.arm.com.
About Calypto
Calypto Design Systems, Inc. empowers designers to create high‐quality, low-power electronic systems by providing best‐in‐class power optimization and functional verification software, based on its patented Sequential Analysis Technology. Calypto, whose customers include Fortune 500 companies worldwide, is a member of the Cadence Connections program, the IEEE‐SA, Synopsys SystemVerilog Catalyst Program, the Mentor Graphics OpenDoor program, Si2 and is an active participant in the Power Forward Initiative.
Calypto has offices in Europe, India, Japan and North America.
More information can be found at: www.calypto.com.

TLM 2.0, UVM 1.0 and Functional Verification

The DVCon 2011 conference was held this week and the Accellera Universal Verification Methodology (UVM) 1.0 release is breaking records in term of interest and attendance.  UVM 1.0 is a big deal(!) The core functionality is solid and ready for deployment.  Accellera held a full day tutorial on UVM 1.0 on Monday.  And during a panel discussion on Tuesday afternoon, AMD and Intel announced that they are in the process of adopting it.

TLM 1.0 ports were heavily used in OVM and in UVM 1.0EA (Early Adopter). The UVM 1.0 release adds a partial SystemVerilog implementation of the Open SystemC Initiative TLM 2.0 capabilities. At DVCon John Aynsley, author of TLM 2.0 spec, did a great introduction of TLM 1.0 and TLM 2.0 concepts and capabilities (one of the best I’ve seen so far for TLM). Later he moved on to UVM TLM implementation both in terms of TLM 1.0 and TLM 2.0, covering the benefits and contrasting it with the OSCI SystemC capabilities. His slide is shown below:

 

The TLM2.0 standard was created for modeling memory-mapped buses in SystemC.  Most of the DVCon discussion was devoted to the concepts of TLM 2.0, with a rich (or complex) set of capabilities. For example sockets and interfaces, blocking and non-blocking transports, the generic payload, hierarchical connection, temporal decoupling and more were covered. The main questions asked were: How much of this is relevant to functional verification and, specifically, UVM environments? What do I need to do differently in a UVM verification environment to leverage the TLM 2.0 potential?

Let’s start by focusing on agents that reside within an interface UVC.  As you can see below, monitors contain analysis ports. The monitor does interface level coverage and checking, and distributes events and monitored information to the sequencer, scoreboard, and other components. Obviously, there is nothing different in UVM from OVM to replace this kind of distributed one-to-many  communication. While this is trivial, this brings us to Guideline # 1: In the monitor, keep using the analysis port.

 

Another communication channel is needed between the sequencer that creates transactions and the driver that sends these to the Device Under Test (DUT). What we have in UVM (introduced in OVM) is a producer/consumer port (uvm_seq_item_pull_port) that has the needed API and hides the actual channels (TLM or others) from the implementation. I know that there was not always an agreement on this by all vendors, but Cadence was constantly recommending users to use this abstract layer, as opposed to the direct TLM ports.  TLM 2.0 sockets do not solve all the communication requirements between the sequencer and the driver (for example try_next_item semantic is hard to resolve in either TLM 1.0 or TLM 2.0).

Also, as was mentioned in the Accellera tutorial, the multi-language support is not solved with UVM 1.0 yet -- and for now, this is a vendor specific implementation. This is a great time to re-iterate our existing recommendation:  Guideline #2:  For sequencer-driver communication, use the abstract producer/consumer ports in your code and avoid using the TLM connections directly. This will keep your code forward compatible with existing or future solutions that the implementation uses (we might need extensions to facilitate cross language communication).  Usage of the high-level functions also allow us, the library developers to add more functionality on get_next_item() and iten_done() calls.  

Another communication layer you may need is for stimuli protocol layering. There are multiple ways to implement layering, but Guideline #2 is valid for this use case as well, where one downstream component need to pull items from a different component. If you stick with the abstract API of the producer/consumer port, you are going to keep your environment safe as we take the liberty of improving the communication facilities for you.

Let’s review other benefits of the TLM 2.0 and the value that they can provide to the verification environment. Again, I include John Aynsley’s slide covering the benefits of TLM 2.0 below. See also my analysis for the individual potential benefits.

 

Let’s review the “value” of these benefits in the context of verification:

• Isn’t TLM 2.0 pass-by-reference capability faster than TLM 1.0, which is is critical for speed?  Indeed, pass by reference is critical for speed and memory usage, but the TLM 1.0 implementation in UVM does not copy by value, so no speed advantages are expected from adopting TLM2.0.

• What about TLM 2.0 support for timing and phases? TLM 2.0 allows defining the transaction status and phases as part of the transaction. NOTE – This is unrelated to UVM phases. This might be a consideration for UVM. I will argue that the timing and status are more important in verification context for the analysis ports and monitors, as this is the channel that is used for such introspection. This can be considered in the next version of the UVM library as part of replacing the underlying implementation of the producer/consumer ports. In general timing annotation in TLM2.0 is complex especially as it is related to “temporal decoupling.” These are too difficult to be used with little return on investment.

• A well defined completion model? We need to think of a use case for this … As we listed all the communication use cases for verification, we could not map this one into a mainstream functional verification need.

• What about the generic payload (GP)? The generic payload is a standard abstract data type that includes typical attributes of memory mapped busses. For example it includes attributes like command, address, data, byte enable and more. An array of extensions exists to enhance this layer with protocol-specific attributes (for example, an AXI transaction defines attributes such as cacheable privileges that are not part of the generic payload definition) .  The generic payload can be used to create protocol independent sequences that can be layered on top of any bus. It is also useful as you communicate to a very abstract model, in early design model before the actual protocols have been decided upon and should be united at some point with the register operation. The generic payload usage does not replace the existing protocol specific sequencer. It also does not lend itself nicely to sequences and randomization as it is hard to constrain the extensions that are stored as array items. To put things in the right perspective, we find the generic payload a good addition to UVM . We used it as part of the Cadence ESL solution and will be happy to share more of our recommendation on the correct usage of the generic payload class. Guideline #3:  check if and how usage of GP can help your specific verification challenges.

• What about the multi-language potential of TLM 2.0? OSCI TLM 2.0, as specified, is a C++ standard. Portions of it cannot be implemented in SystemVerilog nor does it enable or simplify multi-language communication (in fact passing by reference makes it more challenging to support than TLM 1.0). However, what we hear from users is that communicating to high-level models that use TLM 2.0 interfaces is the main requirement of TLM 2.0, which involves multi-language support. As officially stated multiple times in the Accellera tutorial, the multi-language transaction level communication support is not part of the standard library and was left for the individual vendors to support. This will be tricky for users who would like to keep their testbench  vendor-independent. Guideline #4:  Remember that the current UVM TLM 2.0 multi-language support is not part of the standard library and may lock you to a specific vendor and implementation.

To solve this main TLM2.0 requirement, Cadence is working within IEEE 1800 committee to propose extending the DPI to handle passing of objects between different object-oriented languages. Requirements such as passing items by reference or querying hierarchy and others that are not part of TLM 2.0 will be standardized as language features and will hopefully be supported by all vendors. Cadence is working with multiple users that ask for this solution. If you wish to support this effort follow Guideline #5: Join a standardization body or encourage your vendor to support standard multi-language communication  :-)

Summary of recommendations regarding TLM2.0 and verification:

Guideline #1:  In the monitor, keep using the analysis port.
Guideline #2:  Use the abstract producer/consumer ports in your code and avoid using the TLM connections directly.
Guideline #3:  Check if and how usage of GP can help your specific verification challenges.
Guideline #4:  Remember that the current UVM TLM2.0 multi-language support is not part of the standard library and may lock you to a specific vendor and implementation.
Guideline #5: Join a standardization body or encourage your vendor to support standard multi-language communication.

In summary, if you find the TLM 2.0 extensions to UVM to be complex, don't worry, you don't really need to bother with them.  You will probably find the TLM 1.0 communication more than sufficient for most of your testbench development needs.  You might find the Generic Payload useful for abstract modeling of transactions, and you can easily adopt GP without worrying about the rest of the TLM 2.0 complexity.  The main requirement for verifying/integrating SystemC TLM 2.0 models with a SystemVerilog testbench is not yet part of the UVM standard, so we invite you to join the effort to standardize a solution for this problem.

Synopsys Introduces Virtualizer Next-Generation Virtual Prototyping Solution

Highlights:

• Accelerates software development schedules by up to nine months and delivers up to 5X increase in design productivity compared to traditional methods
• Leverages proven virtual prototyping technologies deployed at more than 50 leading semiconductor and electronic systems companies
• Fast and accurate simulation with comprehensive system visibility and control delivers near real-time software execution with unparalleled debug and analysis efficiency
• Integral part of the industry’s most comprehensive solution of tools, models and services for early software development, hardware/software integration, and system validation
• Enables efficient software-driven verification by linking to Synopsys’ HAPS® FPGA-based prototyping systems and VCS® functional verification solution, as well as other environments

MOUNTAIN VIEW, Calif., July 19, 2011 -- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced the availability of Synopsys’ Virtualizer tool set as part of its next-generation virtual prototyping solution. Virtualizer addresses the increasing development challenges associated with software-rich semiconductor and electronic products by enabling companies to accelerate both the development of virtual prototypes and the deployment of these prototypes to software teams throughout the design chain. Prototypes created with Virtualizer allow engineers to accelerate software development schedules by up to nine months, and deliver up to a 5X productivity boost over traditional approaches to teams performing software development, hardware/software integration, system-on-chip (SoC) verification and system validation. 

“As designs increase in complexity and software content to meet the demand for smart devices, companies need to reduce the risk of embedded software project delays and improve developer productivity,” says Steve Balacco, director, embedded software and tools practice, VDC Research. “Synopsys delivers a virtual prototyping solution that directly addresses the debug and analysis needs of embedded software developers in semiconductor and electronic products companies, while bridging the gap with hardware development flows.”

Virtualizer leverages proven technologies from Synopsys’ acquisitions of Virtio, VaST and CoWare as well as expertise gained from deployments at more than 50 leading semiconductor and electronic systems companies. For developers creating a virtual prototype, Virtualizer’s graphical design entry, software debug, and analysis components combined with Synopsys’ broad portfolio of system-level models deliver the fastest time to prototype availability. For software engineers using a virtual prototype of their system to create, integrate, and verify software, Virtualizer Development Kits (VDKs) offer a cost-effective development platform capable of executing unmodified production code at near real-time speed. VDKs provide fast and accurate virtual prototype simulation combined with unmatched multicore-aware software debug and analysis capabilities, concurrent hardware/software analysis, and synchronized debugging with third-party software debuggers and integrated development environments (IDEs). Open and standards-based, Virtualizer supports key industry standards such as OSCI TLM-2.0 and SystemC™ and runs on both Windows and Linux operating systems. 

“Companies deploying virtual prototypes need to easily integrate with existing software development tools,” said Norbert Weiss, international sales and marketing manager at Lauterbach. “The integration of Lauterbach’s TRACE32® with Synopsys’ Virtualizer enables development teams to start software development earlier in a more productive way, as well as expand these benefits from semiconductor to electronic systems companies.”

Virtualizer’s broad set of integration capabilities enables development teams to be more efficient and increase the degree of concurrent engineering in their product development process. Combined with FPGA-based prototyping such as Synopsys’ HAPS systems, Virtualizer facilitates faster SoC validation and software bring up at near real-time performance. Connecting Virtualizer with RTL simulators such as Synopsys’ VCS and emulation platforms such as Eve’s Zebu enables the use of embedded software in hardware verification environments.  Software developers can integrate prototypes based on Virtualizer with their existing debuggers and IDEs, retaining their existing software tool investment. Virtualizer also gives electronic product developers the ability to conduct system validation by networking multiple virtual prototypes together with physical system simulation, testbenches and virtual I/Os. With this broad range of integration capabilities, Virtualizer is uniquely positioned to support the entire electronic supply chain by accelerating development at all stages of the product design cycle.

“With growing hardware complexity, it is critical for verification engineers to start their work as early as possible, and exercise the design with as much real system software as possible,” says Lauro Rizzatti, general manager and marketing vice president of EVE. “The customer-proven integration of Synopsys’ leading virtual prototyping solution and Eve Zebu’s fast emulation platform enables true software-driven scenarios, extending verification coverage and confidence and reducing verification schedules by up to six months.”

“We are focused on helping our customers address their top system-level design challenges: starting software development earlier, accelerating hardware/software integration, and performing full system validation and testing,” says John Koeter, vice president of marketing for IP & systems at Synopsys. “Synopsys’ complete virtual prototyping solution – which includes Virtualizer, an extensive model library, services and support – enables our customers to start software design up to 12 months before first silicon is available. In addition, VDKs cost- effectively enable the development and integration of software throughout the design chain, from IP to SoCs to full systems. At a time of exploding software content at all levels of electronics, Virtualizer enables semiconductor and systems companies to start their software tasks earlier and avoid the risk of surprises late in the development cycle.” 
Availability
Virtualizer is available immediately. Virtualizer Development Kits (VDKs), which incorporate a subset of Virtualizer features specifically targeted for end use cases by software and hardware developers, are also available immediately. For more information, please visit: http://www.synopsys.com/Virtualizer.
About Synopsys
Synopsys, Inc. (Nasdaq:SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys’ comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com.
# # #
Synopsys, VCS and HAPS are registered trademarks of Synopsys, Inc.  All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

The complete destruction of the consumer PC market in the US and Europe is well within Apple’s grasp and will begin to unfold next summer. There is nothing that Intel, Microsoft or the retail channels can do to hold back the tsunami that was first set in motion with the iPad last year and comes to completion with the introduction of one more mobile product and the full launch of the iCloud service for all. The dollars that are left on the table to defend the onslaught are too insufficient to put up a fight. Collapse is at hand.

In the military realm there are plenty of examples of Wars that continue seemingly forever with no side able to gain the upper hand and then in just a matter of months - a sudden collapse due to lack of fighting men, shortages of food and armament and finally a realization that there is no home front left to defend. The American Civil War demonstrated no clear winner until late summer and fall of 1864, when General Sherman marched on Atlanta and then to Savannah, presenting the city to Lincoln as a Christmas present. Along the way he destroyed everything along a 50 mile wide by 250-mile path. Farms, crops, railroads, plantations and the railroad distribution channel were taken out leaving the confederate soldier with nothing to carry on the fight. Suddenly, a collapse.

The full range of Apple products in combination with the ever-expanding number of Apple stores (there are 339 worldwide stores with 56 more coming on line) is sucking the oxygen out of retailers like Best Buy who wonder what they will sell under the big roofs. PCs themselves were never a big profit center for the retailers. It was the accessories that offered huge profit margins. Things like mouses, carrying cases, earphones and especially service agreements were the money winners. But with customers now going to Apple Stores or Apple online, the accessory business moves to Apple. Without this business retailers cut back on the number of PCs they have on display which leads to a distribution problem for PC makers and a natural decline in PC sales.

But this is the least of the worries for PC makers and companies like Microsoft, Google and Intel because in one year Apple will split the MAC Air line to introduce a new product I will call the MAC Air – iCloud. Using the same skins as the MAC Air, the new mobile product with come with an A6 processor and an integrated 3G or 4G wireless solution for access to iCloud from anywhere. The underlying hardware will be similar to what is in an iPAD but with perhaps a little more DRAM to handle productivity Apps that are delivered to the device from the remote iCloud Servers that are x86 based. The MAC Air iCloud is a rendering machine for Office Apps that don’t run on the A6 processor. All other iOS apps will be available to the mobile device.

There are many rumors that Apple will switch the MAC Air to an A6 next year, but this will not be the case. Apple is not ready to take this step, yet. It will open the MAC Air business for bid between AMD and Intel with the bet that the processor cost will decline from $220 today to $75 by mid next year. Look for Intel to hold the business but give Apple the price break it needs to drop entry level MAC Air to $799 from $999 today. The volume will increase dramatically, killing off what is left of the $500-$1000 PC market.

The MAC Air – iCloud will come out at a $399 price for consumers that agree to pay a $25 per month service for at least 24 months in order to gain access to the Office Apps and storing data files on the cloud. Like the iPhone service plans, this one will pull in many customers that may have previously chosen a PC. If you look at the Best Buy data on their web site, the high volume runners all sell for <$449 and the majority sell for $349 - $449. This is the sweet spot of what is left of the consumer PC market. This is why Apple will stick their MAC Air iCloud right in between at $399.

For Microsoft and Intel, this is the end of their consumer market and the business model that sucks out the majority of the dollars. Microsoft still demands $30 per PC O/S royalties and Intel and AMD look to get at least $50-$60 per PC for the processor. With Apple moving customers over to iCloud they get to reap the margins of the entry level consumer who wants to join a better ecosphere that is more secure and offers better mobility and in the end much better, hands on customer support.

Apple will coddle users even more with the iCloud based mobile devices. The retailers don’t stand a chance, which means the PC makers will see distribution channels shrivel. Microsoft, Google, Intel and the rest of the PC supply chain have to think of how to change their business model that gets them as close as a handshake away from their customer.

HP Will Farm Out Server Business to Intel

In a Washington Post Column this past Sunday, Barry Ritholtz, A Wall St. Money Manager and who has a blog called the Big Picture, recounts the destruction that Apple has inflicted on a wide swath of technology companies (see And then there were none). He calls it “creative destruction writ large.” Ritholtz though is only accounting for what has occurred to date. I would contend that we are about to start round two and the changes coming will be just as significant. If I were to guess, HP will soon decide to Farm out its Server Business to Intel. Intel will soon realize that they will need to step up to the plate for a number of reasons.

When HP hired Leo Apotheker, the ex-CEO of Software Giant SAP, the Board of Directors (which includes Marc Andreessen and Ray Lane, formerly of Oracle) implicitly fired the flare guns that they were in distress and were going to make radical changes as they reoriented the company into the software sphere of the likes of Oracle and IBM. To do this, they had to follow IBM’s footsteps by first stripping out PCs. IBM, however, sold its PC group to Lenovo back in 2004 before the last downturn. Unfortunately for HP, it will get much less for its PC business than what they paid for Compaq.

The next step for HP is risky but necessary. They need to consolidate server hardware development under Intel. Itanium based servers are selling at a run rate of $500M a quarter at HP are now less than 5% of the overall server market compared to IBM Power and Oracle SPARC, which together account for nearly 30% of the server dollars. Intel and AMD x86 servers make up the rest (See the chart below). In addition, IBM’s mainframe and Power server businesses are growing while HP’s Itanium is down 10% year over year.

Oracle’s acquisition of Sun always intrigued me as to whether it was meant as a short-term effort to force HP to retreat on Itanium or as a much longer-term strategy of giving away hardware with every software sale. When Oracle picked up Sun, it still held a solid #2 position in the RISC world, next to IBM. By taking on Sun, Oracle guaranteed SPARC’s survival and at the same time put a damper on HP growing more share. New SPARC processors were not falling behind Itanium as Intel scaled back on timely deliveries of new cores at new process nodes. More importantly, the acquisition was a signal to ISVs (Independent Software Vendors) to not waste their time porting apps to yet another platform, namely Itanium. Oracle made sure that HP was seen, as an orphaned child when it announced earlier this year that is was withdrawing support for Itanium.

There is only one architecture, at this moment, that can challenge SPARC and Power and it is x86. It is in HP’s interest to consolidate on x86 and reduce its hardware R&D budget. If needed, a nice software translator can be written to get any remaining Itanium apps running on x86. Since the latest XEON processors are three process nodes ahead of Itanium, there should be little performance difference. But what about Intel, do they want to be the box builder for HP?

I would like to contend that Intel has to get into the box business and is already headed there. There chief issue in holding them back is the reaction from HP, Dell and IBM. Neither of them is generating great margins on x86 servers. With regards to Dell, Intel could buy them off with a processor discount on the standard PC business, especially since they will now be the largest volume PC maker. IBM is trickier.

But why does Intel want to go into the server systems business. The answer is several fold. From a business perspective they need more silicon dollars as well as sheet metal dollars. Intel sees another $20-$30B opportunity in ramping up and they will need it to counteract any flatness or drop in processor business in the client side of the business. Earlier this year, Intel bought Fulcrum, if they build the boxes for the data center, then they have the potential to eat away at Broadcom’s $1B switch chip business.

A more interesting angle is the data center power consumption problem. Servers consume 90% of the power in a data center. It used to be that processors were the majority of the power, but with the performance gap growing between processors and DRAM and the rise of virtualization it now becomes a processor and memory problem. Intel is working on platform solutions to minimize power but they expect to get paid for their inventions.

Intel has started to increase prices on server processors based on reducing a data center’s power bill. Over the course of the next few years they will let processor prices creep up, even with the looming threat of ARM. This is a new value proposition that can be taken one step further. If they build the entire data center box with processors, memory, networking and eventually storage (starting with SSDs), then they can maximize the value proposition to data centers, who may not have alternative suppliers.

In some ways Intel is at risk if they just deliver silicon without building the whole data center rack. There are plenty of design groups at places like Google, Facebook and others who understand the tradeoffs of power and performance and would like to keep cranking out new systems based on the best available technology. By Intel putting down its big foot, it could eliminate these design groups and make it more difficult for a new processor entry (AMD or ARM based) from entering the game.